83 lines
2.8 KiB
Diff
83 lines
2.8 KiB
Diff
diff -Naur a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
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--- a/drivers/gpu/drm/i915/intel_dp.c 2016-01-11 00:01:32.000000000 +0100
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+++ b/drivers/gpu/drm/i915/intel_dp.c 2016-06-11 09:19:14.226982913 +0200
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@@ -3628,8 +3628,7 @@
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intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
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uint8_t dp_train_pat)
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{
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- if (!intel_dp->train_set_valid)
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- memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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+ memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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intel_dp_set_signal_levels(intel_dp, DP);
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return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
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}
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@@ -3746,23 +3745,6 @@
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break;
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}
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- /*
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- * if we used previously trained voltage and pre-emphasis values
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- * and we don't get clock recovery, reset link training values
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- */
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- if (intel_dp->train_set_valid) {
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- DRM_DEBUG_KMS("clock recovery not ok, reset");
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- /* clear the flag as we are not reusing train set */
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- intel_dp->train_set_valid = false;
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- if (!intel_dp_reset_link_train(intel_dp, &DP,
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- DP_TRAINING_PATTERN_1 |
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- DP_LINK_SCRAMBLING_DISABLE)) {
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- DRM_ERROR("failed to enable link training\n");
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- return;
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- }
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- continue;
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- }
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-
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/* Check to see if we've tried the max voltage */
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for (i = 0; i < intel_dp->lane_count; i++)
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if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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@@ -3854,7 +3836,6 @@
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/* Make sure clock is still ok */
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if (!drm_dp_clock_recovery_ok(link_status,
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intel_dp->lane_count)) {
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- intel_dp->train_set_valid = false;
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intel_dp_link_training_clock_recovery(intel_dp);
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intel_dp_set_link_train(intel_dp, &DP,
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training_pattern |
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@@ -3871,7 +3852,6 @@
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/* Try 5 times, then try clock recovery if that fails */
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if (tries > 5) {
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- intel_dp->train_set_valid = false;
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intel_dp_link_training_clock_recovery(intel_dp);
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intel_dp_set_link_train(intel_dp, &DP,
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training_pattern |
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@@ -3894,7 +3874,6 @@
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intel_dp->DP = DP;
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if (channel_eq) {
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- intel_dp->train_set_valid = true;
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DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
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}
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}
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@@ -5157,9 +5136,6 @@
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intel_display_power_get(dev_priv, power_domain);
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if (long_hpd) {
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- /* indicate that we need to restart link training */
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- intel_dp->train_set_valid = false;
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-
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if (!intel_digital_port_connected(dev_priv, intel_dig_port))
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goto mst_fail;
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diff -Naur a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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--- a/drivers/gpu/drm/i915/intel_drv.h 2016-01-11 00:01:32.000000000 +0100
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+++ b/drivers/gpu/drm/i915/intel_drv.h 2016-06-11 09:17:55.457431949 +0200
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@@ -783,7 +783,6 @@
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bool has_aux_irq,
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int send_bytes,
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uint32_t aux_clock_divider);
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- bool train_set_valid;
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/* Displayport compliance testing */
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unsigned long compliance_test_type;
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